The present invention relates in general to etching trenches, and, in particular, to a method for etching trenches in silicon-on-insulator (SOI) or bonded wafer substrates.
Trenches are etched in SOI and bonded wafer substrates to provide isolation between adjacent devices, contact to a buried layer, or both. See, for example, U.S. Pat. Nos. 5,517,047, 5,382,541, and Ser. No. 336,768 filed Nov. 9, 1994 and assigned to the assignee of this application and herein incorporated by reference. While there are many ways of etching trenches, SOI and bonded wafer devices with relatively thick device layers (e.g. 18 microns or greater) present unique problems for device manufacturers. A deep trench exposes the lower corner of the silicon in the device island. When the sidewalls of trenches are oxidized, oxide grown on the bottom corners of the trench generate lattice defects. Oxide growth and corresponding defects can also occur at the top corners of the trench.
One approach to solving this problem as shown in FIGS. IA-ID, removes or rounds the corners. There a bonded wafer structure 10 includes a handle substrate 12, typically of silicon, isolation/bond oxide layer 14, and a device layer 16 of monocrystalline silicon. The device layer 16 is between 17-22 microns thick. A masking oxide layer 18 is grown on top of device layer 16. Photoresist layer 20 is deposited on the masking oxide layer 18 and an opening 22 is formed in the photoresist layer 20. The masking oxide layer 18 is approximately 2 microns thick and the isolation/bonding oxide layer 14 is approximately two microns thick. As a first step the oxide layer 18 is subjected to a wet isotropic etch, typically performed using a solution of hydrofllouric acid, typically a 10:1 solution. This etch creates the isotropic opening 24 in the masking oxide layer 18. Next, the photoresist layer 20 is stripped and a trench 30 is formed using a plasma etch process. A typical plasma etch process uses high power (750 watts) with BC13 as the only active etching agent to remove any residual oxide from the surface of device layer 16. C12 is then added to the plasma reaction in order to etch the trench 30. The mouth of the trench 30, however, has a bevel 26. Some of the isolation/bond oxide layer 14 is also removed. In a final step, the masking oxide layer 18 is removed. During that operation, still more of the isolation/bond oxide layer 14 is removed to leave a groove 28 in the isolation/bond oxide layer 14 at the bottom of the trench. It is often difficult to maintain selectivity between silicon and the thin masking oxide and the etch may remove the masking oxide and thereby expose and damage the surface of the device layer.
Another prior art method is shown in U.S. Pat. No. 5,084,408 issued to Baba et al. In that method a trench is initially anisotropically etched down to the isolation oxide. The isolation oxide is intentionally overetched and a portion of the top oxide mask is also etched in order to expose the corners of the device layer. Next the exposed corners are isotropically etched in order to minimize stress due to known problems inherent in oxidizing square corners at the top and at the bottom of the trench. The method of Baba et al. improves upon the method shown in FIGS. 1A-1D by rounding the top and bottom corners of the trench.
Still others have proposed using different chemistries to etch deep trenches. See, for example, U.S. Pat. No. 4,943,344 which discloses using one or more of SF6, C12, F2, of Br2 in combination with only a photoresist mask to etch a trench in a substrate. All etches are carried out at low temperatures. SF6 alone etches at temperatures of minus 100.degree. C. or less and C12 etches at temperatures of minus 40.degree. C. or less. It is both expensive and time consuming to perform the etches at controlled, low temperatures. U.S. Pat. No. 5,470,781 also discloses using SF6 and C12 to etch a trench in an SOI substrate. However, the latter patent requires further processing steps to remove both the top oxide mask and to round the top corners of the trench.
Accordingly, there has been a long felt need for more efficient method of etching deep trenches. There likewise has been a need for a method of etching deep trenches in SOI and bonded wafer substrates.